40G Coherent Detection

Next generation 40G networks will place an entirely new set of demands on network designers trying to ensure signal reliability. At 40G Chromatic Dispersion (CD) will increase by a factor of ten over 10G levels and Polarization Mode Dispersion (PMD) will be three times worse. Complicating the network design task is the simple fact that all of the key components in today’s existing networks were provisioned for 10G applications. Clearly network designers must find a simple migration path from the existing 10G infrastructure to higher speeds and bandwidth that guarantees performance while minimizing CAPEX costs.

One of the key technologies used to achieve that goal will be coherent detection. First employed in the wireless communications arena, this algorithm improves receiver sensitivity by compensating for optical dispersion using signals proportional to the optical field and employing digital carrier recovery techniques. This methodology mixes the incoming signal for two independent polarizations, X and Y, with a local phase reference or oscillator. The signal is then further decomposed into its I and Q states to provide four independent signals XI, YI, XQ and YQ. These signals contain all the amplitude, phase and polarization information before they are received by the four photo-detectors and converted into digital streams. Once the data stream is recovered, an embedded DSP processor performs clock recovery, equalization, Carrier Phase Estimation (CPE) and recovery functions. As data rates and transmission distances increase, DSP capabilities become increasingly crucial in Coherent systems to overcoming the variety of optical phenomena that pose an obstacle to network performance.

Leveraging the company’s industry-leading EDC technology in 10G systems, ClariPhy is developing Coherent-based solutions that will serve as a benchmark for next-generation 40G and 100G optical networks. The new ICs will take advantage of ClariPhy’s extensive experience in advanced DSP algorithms and its highly integrated systems architecture to offer a single platform for 40G and 100G applications. As a result network equipment designers will be able to use the same chip architecture, with the same FEC, pin out and firmware to develop both 40G and 100G solutions. They will also be able to take advantage of the architecture’s lower sensitivity to impairments to double the reach of network segments. Finally, the unique power dissipation characteristics of ClariPhy’s all-CMOS solution will allow service providers and equipment developers to bring dramatic power savings to a new generation of high performance network equipment.