ClariPhy Technology

Today’s Metro and Long Haul networks and datacenters are facing an avalanche of video, voice and data. Driven by the rapid rollout of triple play services and escalating growth in the smart phone and broadband markets, telecom and enterprise network architects are scrambling to plan a faster-than-expected migration to 10G, 40G and, ultimately, 100G networks using existing fiber.

To facilitate that build out, ClariPhy has developed the first single-chip CMOS architecture for EDC ICs to offer a simple, scalable path to 100G performance.  Unlike multi-chip alternatives using exotic processes, ClariPhy’s new technology is the only solution in the industry to combine mixed-signal processing (MXSP) with high performance analog and digital signal processing (DSP) functions on a single die fabricated in industry-standard 40 nm CMOS. This unique implementation enables ClariPhy engineers to deliver MLSE and Coherent Detection algorithms as well as FEC/ECC codes – the key functions needed to enable 10G, 40G and 100G networks – in the same CMOS silicon platform.

The advantages for telecom and enterprise network equipment designers are dramatic. As service providers and enterprises move to higher network transmission levels, impairments such as chromatic dispersion (CD) and polarization mode dispersion (PMD) pose significant obstacles. To compensate for these impairments, network architects must deploy expensive dispersion compensation equipment (DCE), compensation fiber, ROADM, and Regen to boost transmission. At the same time higher performance networks require more frequent service calls to optimize fiber segments.

Using its integrated MXSP and highly flexible on-chip DSP capabilities, ClariPhy can enable MLSE and Coherent Detection algorithms that diminish sensitivity to these common impairments and dramatically reduce the complexity and cost of next generation network implementations. In 10G networks MLSE-enabled EDC ICs can significantly reduce CAPEX costs by eliminating costly DCE, compensation fiber, ROADM and Regen. At the same time, ClariPhy’s unique MLSE solutions enhance OSNR and CD performance by up to 3 dB boosting network reach by as much as 4X with a clean eye. The resulting lower parts count and improved network reliability lowers field service calls and network OPEX.

Just as important, ClariPhy can scale the same common CMOS architecture for use in next-generation 40G and 100G networks. Using the same AFE and DSP blocks and soft decision iterative codes such as GFEC, ClariPhy engineers can build Coherent Detection-enabled EDC ICs that support the tough performance requirements of 40G and 100G transmission.

This single, scalable CMOS architecture offers telecom and enterprise network equipment designers unparalleled benefits. As they migrate up the transmission chain they can reap the same advantages in terms of OSNR performance, reach, improved reliability and lower cost. As an example, fiber with a PMD of 0.5 ps/km2 in a conventional 50G system can only reach 50 Km, while ClariPhy’s solution will extend approximately 2,000 Km. At the same time the use of the same proven silicon architecture dramatically speeds development and shortens time-to-market. Engineers working with the same familiar silicon can reduce development time and beat competitors to market. Finally, the use of an integrated single chip solution fabricated in an industry standard 40 nm process promises significant power savings. ClariPhy estimates those savings could reach up to 50% over multi-chip alternatives using more exotic IC technologies.