ClariPhy has delivered the world's first all-digital, CMOS based 10 Gbit/s maximum likelihood sequence detection (MLSD) solution.  At four times faster than state-of-the-art, this innovative MLSD architecture combines digital signal processing and digitally-calibrated analog circuitry to simultaneously optimize performance and power dissipation.

MLSD is proven to be the theoretically optimal receiver employing algorithms that evaluate a sequence of incoming data to determine the most likely correct sequence.  This advanced process improves the performance of networks by minimizing data errors or corruption. Ubiquitously used in lower speed applications, ClariPhy is the first to introduce CMOS based MLSD products for use at 10 Gbit/s and above. 

ClariPhy's advances in communications IC development:

• Industry's first all-digital CMOS 10 Gbit/s MLSD based EDC* solution that exceeds the stringent cost, power, reach, and latency requirements of enterprise networks
• Digitally calibrated analog design, enabling 10 Gbit/s digital signal processing while achieving the low power dissipation required by enterprise PHY applications
• High-performance, low-power digital signal processor (DSP), comprising a feed-forward equalizer (FFE) and maximum likelihood sequence detection (MLSD)
• Standard digital CMOS process technology leveraging CMOS and Moore's Law

*NOTE:  ClariPhy's MLSD technology is an advanced form of electronic dispersion compensation (EDC) used to compensate for the impairments found in fiber networks.  

To read more about ClariPhy's technology, please request the following ClariPhy white paper, "A Technology Roadmap: 10 Gigabit Ethernet and Beyond" by submitting the form below.