Highly Integrated Solutions for Networking SoC’s
As network transmission rates increase, network equipment designers need low-cost, low-power solutions that extend reach and minimize signal impairment across high performance networks. At the same time, demand will increase for highly specialized solutions that are optimized for specific performance, power or cost requirements. A standard product approach may not be the optimal choice for a system integrator with internal DSP design capabilities, differentiated IP cells, and system know-how seeking a custom IC solution. As a system-on-chip (SoC) partner you can trust, ClariPhy is experienced in overcoming chip complexity and integration issues, minimizing die size for optimal cost, providing full back-end services, determining optimal packaging configuration, neutralizing multiple supplier issues, and implementing production test, while managing the overall project from start to qualified, high volume silicon. ClariPhy is unique in the industry as a merchant semiconductor supplier of SoCs seamlessly developed using 40 nm CMOS with MXSP technology for high performance applications.
To meet the growing need, ClariPhy is developing new partnerships in which it will integrate its innovative technology with partners’ technologies in order to create new ASICs and SoCs. By leveraging its extensive experience with the integration of an analog front end (AFE), high performance DSP, and ultra-high performance interface circuit capabilities onto a single die, ClariPhy offers a wide range of functional blocks it can combine with specialized technologies to meet emerging market needs. ClariPhy engineers are responsible for physical implementation including floor planning, cell placement, clock tree insertion, routing (power and signal), and other IP support. ClariPhy offers both existing and new partners access to TSMC 40 nm CMOS, acces to our extensive IP library, high speed analog and digital design resources, backend engineers, project managers, and operations team all ensuring a positive silicon experience.
Some of the common IP blocks available from within ClariPhy’s MXSP SoC library include:
IP |
Names |
Support |
AFE |
Analog Front End |
Multi-Channel ADCs in CMOS |
CGU |
Clock Generation Unit |
Timing Recovery, GHZ |
DSP |
Digital Signal Processor |
MLSE, Coherent |
FEC |
Forward Error Correction |
HD and SD FEC with Wrappers |
SerDes |
Serializer/Deserializer |
Multi-banks and lanes |
Memory |
SRAM |
As Required |
Interfaces |
Host/Client Interface |
Linear, SFI5.1, XFI, RXUAI, OTL4.10, etc. |
I/O |
Input/Output |
CMOS, LVDS (multiple voltages) |
Control |
Microcontroller I/F |
I2C, SPI |
BIST |
Test Structures |
Supported |
Packaging |
External Package |
Custom with Heat Sink |
Supports 10/40/100G Applications |
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ClariPhy simplifies the process of product development by taking our customer’s conceptual ideas and turning them into production products using our MXSP SoC design methodology. ClariPhy utilizes industry standard EDA tools and common design flow methodologies to seamlessly integrate our customer’s IP into a SoC solution. The ClariPhy SoC Design Flow diagram provides a top level view of the common tasks associated with developing a leading edge, high performance SoC IC.
