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ClariPhy Company Contact: ClariPhy Media Contact:
John O’Neill Lauri Julian
Vice President, Marketing ClariPhy Public Relations
949-922-8658 949-715-3049
john.oneill@clariphy.com l.julian@mediaconnectpr.com
CLARIPHY COMMUNICATIONS DEMONSTRATES ALL-DIGITAL EDC TRANSCEIVER BASED ON MLSD TECHNOLOGY AT OFC/NFOEC 2007
Optimal Transceiver Architecture Exceeds 10GBASE-LRM Requirements; Enables Next Generation SFP+ Optical Modules
IRVINE, Calif., March 22, 2007 – ClariPhy Communications, Inc., a fabless semiconductor company specializing in high speed communications ICs, today announced that it will demonstrate its 10GBASE-LRM integrated circuits (ICs) with industry leading performance at the OFC/NFOEC conference (www.ofcnfoec.org) in Anaheim, California on March 25-29, 2007. ClariPhy will showcase an all-digital CMOS IC comprising a 10-gigasample per second Analog to Digital Converter (ADC) and a Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) engine. The demonstration will include industry defined worst-case 300-meter fibers and low-cost SFP+ optical modules from industry leaders such as ExceLight Communications and Picolight.
A digital MLSD architecture has been proven to enable optimal receiver performance for bandwidth-constrained media such as legacy multi-mode fiber in enterprise backbones. Because of the complexities of IC design at rates of 10Gbits/sec, EDC technology for this application has until now been implemented with suboptimal analog equalization techniques. Analog equalization suffers from fundamental limitations inherent in analog signal processing, including process-dependence of device parameters, noise sensitivity, and implementation non-idealities.
In response to the demand for a better performing product, ClariPhy has developed an all-digital CMOS solution integrating a low power 10-gigasample per second ADC and MLSD engine. The all-digital architecture overcomes the limitations of analog architectures by utilizing underlying signal recovery algorithms that are proven to be optimal for the application. The result is predictable and stable performance near the theoretical limit.
“Our engineering team has delivered breakthrough technology that few believed possible,” said Dr. Paul Voois, founder and CEO of ClariPhy. “In developing the first MLSD transceiver for 10GBASE-LRM applications, we have extended the state of the art in numerous areas of IC architecture, VLSI implementation, and mixed-signal design and layout. In addition, history has shown that an all-digital CMOS approach outperforms analog alternatives for challenging communications applications. ClariPhy is proud to be the leader in the transition of EDC technology to all-digital architectures, and we are confident that our technology will significantly raise industry standards of performance for 10GBASE-LRM and SFP+ applications.”
ClariPhy will demonstrate its MLSD and enabling ADC technology in a private suite at the OFC/NFOEC conference (www.ofcnfoec.org) in Anaheim, California on March 25-29, 2007. The demonstration will include 10GBASE-LRM data transmission over worst-case 300-meter fibers and SFP+ modules. ClariPhy invites interested parties to contact John O’Neill, VP of Marketing at 949-922-8658 or john.oneill@clariphy.com.
About ClariPhy
ClariPhy Communications, Inc. is a fabless semiconductor company developing high-speed ICs targeting 10-Gbit/s networks in enterprise backbone and enterprise data center environments. ClariPhy’s ICs enable IT management to significantly improve enterprise network performance and lower cost. ClariPhy has secured Series A financing led by Norwest Venture Partners (NVP), with participation from Onset Ventures, Allegis Capital and Pacific General Ventures. ClariPhy has executive offices in Irvine, California and a development center in Cordoba, Argentina. For more information, please visit www.clariphy.com.
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