ClariPhy Communications to Present at Linley Group High Speed Interconnect Design Seminar

May 6, 2008

ClariPhy announced that John O'Neill, Vice President of Marketing, will present at the Linley Tech High-Speed Interconnect Seminar on May 14^th, 2008 in San Jose, CA. ClariPhy's presentation will provide a retrospective overview of the 10G optical market and highlight the density, power, flexibility and cost advantages SFP+ has over alternative copper solutions. Furthermore, the presentation will illustrate ClariPhy's highly differentiated, digital CMOS based Maximum Likelihood Sequence Detection (MLSD) 10G PHY solutions. ClariPhy is the first and only supplier of fully integrated CMOS based MLSD solutions for Enterprise and Telecom applications.

Ethernet Alliance Members Hold Successful Interoperability Demonstration of SFP+ Optical Interfaces

April 21, 2008

The Ethernet Alliance recently announced that members, including ClariPhy successfully conducted multi-vendor interoperability testing of Small Form Factor Pluggable (SFP+) short-reach (10GBASE-SR) and long-reach (10GBASE-LR) optical interfaces. The testing, held by the Ethernet Alliance SFP+/EDC subcommittee, demonstrated multiple SFP+ SR and LR optical transceivers and physical layer (PHY) ICs interoperating over 270 meters of OM3 multimode fiber and 10 km of single-mode fiber. In addition, the group demonstrated multiple SFP+ SR and LR optical transceivers and PHY ICs interoperating with XENPAK, X2, and XFP optical transceivers over the same distances.

SFP+ modules are hot-pluggable, small-footprint optical transceivers intended for datacom applications. SFP+ interfaces offer the smallest, lowest-power solution for 10 Gigabit Ethernet (10GbE) to enable increased density in enterprise applications. SFP+ modules and PHY ICs are being developed for SR, LR, LRM (long-wavelength multimode) and ER (extra-long-wavelength) optical reaches per IEEE Std. 802.3ae-2002 and IEEE Std. 802.3aq-2006. Electrical and mechanical interface specifications for SFP+ modules, direct attach cables, and hosts are under definition by the SFF Committee, a multi-source agreement group with broad industry participation.

"We expect the move to smaller SFP+ modules will help increase the port density and reduce the cost of 10 Gigabit Ethernet line cards," said Jag Bolaria, senior analyst, Linley Group. "Demonstrating interoperability between 10GBASE-SR and 10GBASE-LR SFP+ modules with existing XENPAK, X2 and XFP modules showcases the readiness for deployment of SFP+ modules."

ClariPhy Communications Denonstrates Second Generation EDC Transceiver Based on MLSD Technology at OFC /NFOEC 2008 

February 20, 2008

ClariPhy announced that it will demonstrate its 10Gbit/s integrated circuits (ICs) with industry leading performance at the OFC/NFOEC conference to showcase a second generation all-digital CMOS Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) engine.

ClariPhy has previously demonstrated the advantage of a digital MLSD architecture for bandwidth-constrained media such as legacy multi-mode fiber in enterprise backbones. As the only supplier of

10Gbit/s MLSD based ICs, ClariPhy has leveraged the availability of advanced CMOS technologies to provide unmatched performance while meeting the stringent power budget of next generation data center and enterprise networking equipment.

"We introduced our MLSD-based transceiver at OFC 2007 and established a new standard for 10Gbit/s EDC performance," said Dr. Paul Voois, cofounder and CEO of ClariPhy. "Our second generation transceiver delivers even better performance at significantly lower power, demonstrating one of the key advantages of the all-digital CMOS approach, which is the exponential reduction in power and cost achievable via Moore's Law. History has shown that all-digital CMOS is the winning technology in high-volume communications applications such as Ethernet. By delivering industry-best performance, ClariPhy has established a unique and highly differentiated advantage for 10Gbit/s EDC applications."

ClariPhy to participate in the 2008 International Solid State Circuits

January 31, 2008

ClariPhy’s chief technology officer and co-founder, Dr. Norm Swenson and its vice president and chief systems architect, Dr. Oscar Agazzi, will present at three separate sessions at the ISSCC February 3-7, 2008. 

In a conference session on optical communications, Dr. Agazzi will present a peer-reviewed paper entitled “A 90nm CMOS DSP MLSD Transceiver with Integrated AFE for Electronic Dispersion Compensation of Multi-mode Optical Fibers at 10Gb/s.” This paper describes ClariPhy’s 10GBASE-LRM transceiver IC, available since February 2007.  This IC is the only MLSD (maximum likelihood sequence detection) based product available for 10GBASE-LRM and the only monolithic 10Gb/s MLSD IC

At a special topic session entitled “Trends and Challenges in Optical Communications Front-End,” Dr. Swenson will give an invited presentation on the transition of 10Gb/s Electronic Dispersion Compensation (EDC) from analog to DSP-based CMOS solutions.  He will focus on the challenges of that transition, the enabling technologies that meet those challenges, and the benefits thereby achieved.

Additionally, in a design forum focusing on the future of high speed transceivers, Dr. Agazzi will provide an invited tutorial entitled “DSP-Based Optical Transceivers for Electronic Dispersion Compensation of Single-Mode and Multimode Fibers.”

Metro Ethernet Boom Fuels Growth in 10-Gbit/s Components Market, New Report Finds

ClariPhy to Demonstrate it's MLSD-based EDC for Next Generation Telecommunication Applications at ECOC 2007

September 14, 2007

ClariPhy announced that it will demonstrate its all-digital CMOS Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) at ECOC 2007, Europe’s largest optical communications event.

ClariPhy Communications Enters 10G Telecom Market with Advanced Maximum Likelihood Sequence Detection Technology

September 13, 2007

ClariPhy has expanded its market focus to include 10G telecommunications (telecom) networks. ClariPhy's Maximum Likelihood Sequence Detection (MLSD) based Electronic Dispersion Compensation (EDC) engine, implemented in a single-chip CMOS form factor, is perfectly suited to enable data rate increases from 2.5G to 10G in carrier networks cost-effectively and without sacrificing performance or reach. Based on estimates from industry analyst firm CIR, optical transponder shipments are expected to grow by almost 40% per annum over the next five years, with the total dispersion compensation market reaching $755 Million by 2012.

ClariPhy has completed product evaluations with the industry's leading optical transponder vendors. Based on this activity, ClariPhy has defined a family of products which will enable vendors to leverage MLSD to complement the technologies they have pioneered such as advanced lasers and modulators, advanced modulation techniques, and emerging transponder form factors for the diverse set of telecom market segments.

ClariPhy’s Integrated CMOS MLSD Engine Creates Large Market Expansion Opportunity

September 13, 2007

Carriers today seek to upgrade their optical networks to 10G while simultaneously improving performance and lowering the overall cost of installing and maintaining these networks.  EDC technology is being rapidly integrated into 10G equipment based on its ability to improve performance through impairment mitigation.  Specifically, MLSD-based EDC enables the use of lower cost optical components and extends the reach of optical links through the compensation of impairments found in the components and fiber optic cabling.

Lawrence Gasman, CIR President and Chief Components Analyst commented: “In our recent report ‘Opportunities in Dispersion Compensation: Electronic, Optical and Tunable,’ we highlight the increasing importance of dispersion compensation and the need for higher performing dynamic dispersion compensation. EDC components including ClariPhy’s CMOS MLSD device have a compelling proposition and are well timed for the emerging opportunity in metro, long haul, and ultra long haul networks.”

According to ClariPhy’s CEO, Dr. Paul Voois, “Our engineering team has extensive experience in telecom product development.  Entering the telecom market represents a logical expansion of our initial enterprise focus, while building upon our core value proposition of using CMOS-based digital signal processing to reduce the cost and improve the performance of optical communications. We have demonstrated significant performance advantages in enterprise applications and we expect to do the same in the telecom space.”

ClariPhy Leverages Helic's VeloceRF EDA Tool for First-Pass Success of CMOS 10G Mixed-Signal IC

June 15, 2007

ClariPhy Communications and Helic S.A. have announced details of their joint engineering collaboration over the past 12 months, which has been instrumental in the first-pass success of ClariPhy's single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. ClariPhy's transceiver features a low-power 10G Analog to Digital Converter (ADC) and a Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) engine.

ClariPhy recently demonstrated its 10GBASE-LRM integrated circuit (IC) with industry-leading performance at OFC 2007. In response to the demand for a better performing product, ClariPhy has developed an all-digital CMOS solution integrating a low power 10G ADC and MLSD engine. The all-digital architecture overcomes the limitations of analog architectures by utilizing underlying signal recovery algorithms that are proven to be optimal for the application. The result is predictable and stable performance near the theoretical limit.

"We knew from the start of this project that success depended on executing beyond the state of the art in mixed signal IC design," said Dr. Paul Voois, ClariPhy's CEO. "The engineering collaboration with Helic was instrumental in our first-pass design success. ClariPhy has pioneered the migration to an all-digital 10-Gbit/s PHY, and Helic's tool allowed us to implement our advanced product architecture with confidence."

ClariPhy and Helic Announce Details of their Joint Engineering Collaboration  

June 4, 2007

ClariPhy selected Helic’s EDA tool, VeloceRF, after diligent evaluation to aid in the first-pass success of ClariPhy’s single-chip, 10GBASE-LRM, mixed-signal CMOS transceiver. ClariPhy’s transceiver features a low-power 10G Analog to Digital Converter (ADC) and a Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) engine.

The main requirement was synthesis and modeling of spiral inductors, but ClariPhy’s designers found the Helic tool also valuable as an inductive parasitics (RLCK) extractor.  VeloceRF was used to synthesize and model all the inductive content of the chip, including on-chip inductors and several critical, high-speed interconnects.   VeloceRF enabled ClariPhy’s designers to optimize circuit performance while minimizing silicon real estate. With inductance accurately calculated by VeloceRF, it was possible to mitigate detrimental effects before tapeout, and achieve excellent performance in first-pass silicon.

“We greatly enjoyed working with the ClariPhy team,” said Sotiris Bantas, vice president of technology at Helic. “They leveraged the tool’s capabilities and latest features, including spiral component synthesis in CMOS and inductance/mutual inductance extraction for accurate 10 GHz simulations. ClariPhy is already a marquee customer for us, demonstrating VeloceRF as a winning methodology for high-speed and RF nanoscale CMOS design.”

ClariPhy to demo all-digital EDC transceiver based on MLSD technology at OFC/NFOEC

March 23, 2007

ClariPhy Communications Inc. will demonstrate its 10GBASE-LRM integrated circuits (ICs) at next week's OFC/NFOEC Conference in Anaheim, CA.

ClariPhy says it will showcase an all-digital CMOS IC comprising a 10-gigasample/sec analog-to-digital converter (ADC) and a Maximum Likelihood Sequence Detection electronic dispersion compensation (EDC) engine. The demonstration will include industry-defined, worst-case 300-meter fibers and low-cost SFP+ optical modules from such vendors as ExceLight Communications and Picolight.

ClariPhy Communications Demonstrates All-Digital EDC Transceiver Based on MLSD Technology at OFC/NFOEC 2007

March 22, 2007

In response to the demand for a better performing product, ClariPhy has developed an all-digital CMOS solution integrating a low power 10-gigasample per second ADC and MLSD engine. The all-digital architecture overcomes the limitations of analog architectures by utilizing underlying signal recovery algorithms that are proven to be optimal for the application. The result is predictable and stable performance near the theoretical limit.

"Our engineering team has delivered breakthrough technology that few believed possible," said Dr. Paul Voois, founder and CEO of ClariPhy. "In developing the first MLSD transceiver for 10GBASE-LRM applications, we have extended the state of the art in numerous areas of IC architecture, VLSI implementation, and mixed-signal design and layout. In addition, history has shown that an all-digital CMOS approach outperforms analog alternatives for challenging communications applications. ClariPhy is proud to be the leader in the transition of EDC technology to all-digital architectures, and we are confident that our technology will significantly raise industry standards of performance for 10GBASE-LRM and SFP+ applications."

ClariPhy Communications Presents 10G Ethernet Physical Layer Compliance Testing Fundamentals at OFC/NFOEC 2007

March 22, 2007

ClariPhy Communications announced that Dr. Norm Swenson, founder and CTO, will present a paper on the IEEE 802.3aq (10GBASE-LRM) adopted Transmitter Waveform and Dispersion Penalty (TWDP) test methodology at the OFC/NFOEC conference (www.ofcnfoec.org) in Anaheim, California on March 25-29, 2007.

Dr. Swenson will address how the incorporation of Electronic Dispersion Compensation (EDC) technology in optical networking presents new challenges in compliance testing. The paper describes the 10GBASE-LRM TWDP test and procedure, discusses the motivation for this type of test, and provides supporting mathematical details of the underlying algorithm.

“From ClariPhy’s inception, we have focused on enabling low cost 10Gbit/s Ethernet on existing infrastructure,” said Dr. Norm Swenson, founder and CTO of ClariPhy Communications. “A test methodology that ensures interoperability among low-cost solutions was a major challenge that we have spent considerable effort addressing.”

The mighty micro-multinational

The garage goes global as a new breed of startup operates worldwide in the battle for technology, talent, and customers.

by Michael V. Copeland, Business 2.0 Magazine senior writer
July 28 2006

Oscar Agazzi is the magic expatriate at Irvine, Calif., chip startup ClariPhy, where he is chief systems architect. About 18 months ago, the native Argentinean and Broadcom veteran proposed to ClariPhy CEO Paul Voois that they hire a team of graduates from Argentina's National University of Cordoba.
Why Argentina? The country has lots of talent but less competition for top engineers than tech hot spots to the north. That made it relatively easy for Voois and Agazzi to make the 18-hour trip from Southern California to South America and pluck eight of the best candidates for about a third the cost of hiring homegrown talent.

"We can set a very, very high bar for the people we recruit," Voois says. "And it's not a cost thing so much as the ability to hire more people for the same money. Because of that, we will have gotten to market faster and with a better product than if we had tried to do it all in Irvine."

But make no mistake about it: This wasn't about heading south for some hit-and-run code crashing. Argentina became an extension of ClariPhy's operation and the South Americans an integral part of its team. For Agazzi, that initially meant going back and forth on planes and the phone, acting as a middleman and, in some cases, literally as a translator between the two hemispheres.

He brought the Argentinean engineers to Irvine for extended visits and made sure the team not only had interesting work to do but also delivered on its tasks. "We have developed a common culture that spans both teams and both countries," Agazzi says. "That is a very powerful concept that can grow along with this global company we are building."

Fabless comms IC firm establishes Argentinean design center

By Dylan McGrath
6/21/06

Fabless communications semiconductor provider ClariPhy has completed the incorporation of its Argentinean development center in Cordoba. Billed by some as the "Silicon Valley of South America," Cordoba is the site of development centers for a number of prominent companies. The nearby National University has more than 100,000 students and, according to ClariPhy, offers a "relatively untapped pool for engineering talent."

Oscar Agazzi, ClariPhy corporate vice president and chief systems architect as well as president and CEO of ClariPhy Argentina S.A., called ClariPhy's move to establish a design center in Argentina “progressive."

Agazzi, an Argentinean native, said, "This is an exciting opportunity to work on some of the most advanced technologies in the communications industry."

Local chip maker opens design center in Argentina

By Tamara Chuang
6/21/06

ClariPhy has added a design center in Argentina to speed up development on communication chips for 10-gigabit technology. The facility near the National University of Cordoba will double ClariPhy's design capabilities.

The area was chosen because there's only a four-hour time difference with the Irvine headquarters compared with time differences of 12 hours for India and 15 hours for China. Also, the local university has thousands of students and is "a relatively untapped pool for engineering talent," a company statement said.

The company builds chips for 10-gigabit-per-second communication networks, a niche that will allow for faster Internet speeds.

ClariPhy Communications doubles up -- in Argentina

6/21/06

ClariPhy has completed the incorporation of its Argentinean development center near the National University of Cordoba. The development center doubles ClariPhy's design capabilities and accelerates development of 10-Gbit/sec mixed signal and other high-speed ICs.

"ClariPhy is built on world-class engineering talent. The team assembled in Argentina has made a significant contribution to the development of our first product, a 10-Gbit/sec physical-layer device for use on installed multimode fiber networks," said Dr. Paul Voois, president and CEO of ClariPhy. "Based on its history of execution and on the exceptional engineering talent in Cordoba, I am confident that our team there will continue to play a key role in ClariPhy's success."

Glimmer of 10G unity casts fiber in new light

By Loring Wirbel
4/24/06

Moving certain portions of electronics outside the transceiver module could allow for more efficient use of dispersion compensation and clocking, since one device could serve multiple ports. Newcomer ClariPhy Communications Inc. is using SFP+ for its EDC chips as a differentiator in a dispersion compensation market already under aggressive attack by others. ClariPhy will pitch SFP+ in such emerging Ethernet markets as LRM, the long-reach standard for multimode fiber, and the LR and SR standards for achieving long and short reaches over single-mode fiber.

Chip vendors line up for EDC business

By Stephen Hardy
4/1/06

These entrenched IC providers will see competition from ClariPhy Communications Inc. (Irvine, CA). Unlike most EDC offerings for the LRM space that use some form of decision feedback equalizer (DFE) and/or feed forward equalizer (FFE), ClariPhy will pair FFE with maximum likelihood sequence estimation (MLSE). MLSE has been used successfully by companies such as CoreOptics for single-mode applications, but ClariPhy CEO Paul Voois says his crew has found a way to apply it economically to multimode requirements. The CMOS based device should begin sampling by the end of this year's third quarter, Voois says.

10-Gigabit Ethernet camp eyes SFP+

By Meghan Fuller
4/1/06

With every new Ethernet speed, data rates tend to increase by a factor often, which typically results in a price premium for new modules. Fibre Channel data rates, by contrast, merely double with each new speed. Folks in the Fibre Channel world, therefore, are accustomed to purchasing new modules at newer rates for roughly the same price or at only a slight premium over existing modules.

"In the past, the way people have attacked that is to put more silicon in the module," notes Norm Swenson, CTO of ClariPhy Communications (Irvine, CA). "The XFP, for example, has a retimer inside the module in both the transmit and receive directions. But when you start adding those components inside the module, you start adding cost that the Fibre Channel community was not that eager to adopt."

10 Gigabit Ethernet Costs to Drop

By John G. Spooner
2/20/06

A new generation of networking chip startups is attempting to find a path into businesses' networks by making 10 Gigabit Ethernet networking gear more palatable to their technology budgets.

ClariPhy plans to offer a chip that can save companies money by bumping the bandwidth of existing network cables. Based on a DSP (digital-signal processor), its physical layer interface chip for 10 Gigabit Ethernet most likely will be built into line cards used by network switches. The chip will make it possible for companies to continue using their existing 2.5G-bps multimode optical network cables, but it promises to bump the bandwidth of those cables to 10G bps.

Making Gig to 10Gig a seamless step

Can cheaper technology for 10Gig fibre displace copper LANs in our hearts?

By Bryan Betts
2/17/06

ClariPhy is developing what CEO Paul Voois claims will answer to the upgrader's dilemma - a PHY (physical interface) chip for fibre optic networking that will enable today's multimode fibre installations to be upgraded to 10Gig via the upcoming 10GBase-LRM standard. Not only will 10Gig over LRM be cheaper than today's LX4 spec for 10Gig fibre, he argues, but it will go further than the 10GBase-T spec for 10Gig over copper and generate less heat too.

Chip Makers Pitch 10 Gigabits on the Cheap

By John G. Spooner
2/14/06

The chip (to be offered by ClariPhy), which will conform to the forthcoming IEEE 10GBase-LRM standard for 10 Gigabit Ethernet over optical cables, "is able to offer the increase (in bandwidth) because its built-in digital-signal processor can compensate for distortions created by sending the high-speed signals," said Paul Voois, ClariPhy's CEO, in Irvine, Calif.

"What's going to save them cost going to 10 Gigabit is not having to replace their cable," Voois said.

Chip Makers Pitch 10 Gigabits on the Cheap

By John G. Spooner
2/13/06

Following the 10GBase-LRM standard means companies can cut costs by employing fewer lasers for sending networking signals via optical cables than current chips based on than today's 10GBase-LX4 standard. "But ClariPhy's secret sauce is in the way it employs its electronic dispersion compensation techniques, making use of the DSP to compensate for signal distortion, in addition to using CMOS, a standard method for manufacturing processors, memory and other chips," Voois said.

OPTICAL NETWORKS: Chip preps for SFP+ standard

By Loring Wirbel
2/13/06

ClariPhy is aiming its upcoming electronic dispersion-compensation (EDC) chip at SFP+, the industry's emerging small-form-factor pluggable optical-module standard. "The SFP+ standard is critical," said ClariPhy chief executive Paul Voois. Originally promoted by Fibre Channel advocates as a follow-on to the SFP module used at lower speeds, SFP+ is now seen as appropriate for 10-Gbit Ethernet using the LRM (long-range multimode), SR (short-reach) or LR (long-reach) fiber standards.

"There were also plenty of startups working in dispersion-compensation areas, so we had to show we had something unique," Voois said. "We consciously focused on fiber in the enterprise, instead of public metro applications. And we avoided the XFP module market, because with XFP, you had to leave the EDC functions in the module or you could not equalize the channel."

XFP Module Gets a Shrink

Craig Matsumoto, Light Reading
2/10/06

"The smaller size of SFP+ could also boost linecard density to at least 24 ports per card from 16 with XFP," says Paul Voois, CEO of chipmaker ClariPhy Communications Inc. But wait, there's more: Putting the electronics outside the module also opens the possibility of serving multiple lines per module, the way Gigabit Ethernet does. "That's how you really drive down costs," Voois says.

XFP module gets a shrink

Craig Matsumoto, Light Reading
2/10/06

Chip vendors and optics suppliers are crafting the next transceiver standard for 8-Gbit/s Fibre Channel and possibly 10-Gbit/s Ethernet, one that could eventually supplant XFP modules. It's being called SFP+ -- a smaller module than XFP. It removes electronics such as a chip for clock and data recovery, putting them on the linecard instead. This lets the module shrink to the size of the small-form pluggable (SFP) used for 2.5-Gbit/s ports.

XFP Module Gets a Shrink

Craig Matsumoto, Light Reading
2/9/06

SFP+ would be a smaller module than XFP. It removes electronics such as a chip for clock and data recovery, putting them on the linecard instead. This lets the module shrink to the size of the small-form pluggable (SFP) used for 2.5-Gbit/s ports.

Why does that matter? For starters, the engineering is easier when things are added to a linecard, as opposed to the module. A shift to SFP+ could lower the cost of optical modules.

Newcomer ClariPhy reveals plan for reducing fiber costs

By Jeff Caruso
2/7/06

This week marks ClariPhy's official debut, and company is claiming to have developed the first DSP-based PHY for 10Gbps over fiber using a CMOS process. ClariPhy is hanging its hat on 10GBase-LRM, which is close to becoming an IEEE standard. It uses a single laser and set of optics, rather than the four lasers and four sets of optics of the earlier 10GBase-LX4 standard.

ClariPhy is also using CMOS to get the cost down, and is looking to the SFP+ serial form factor as well. CEO Paul Voois says he expects Cisco to go from XAUI to a serial interface, and that the rest of the industry will follow, creating a market for SFP+ and breaking the "cost barriers."

ClariPhy clarifies market direction, touts technology advancements

By Meghan Fuller
2/6/06

ClariPhy's initial product will be a 10-Gigabit Ethernet (10GbE) PHY targeting the emerging 10GBase-LRM Ethernet standard, nearing IEEE ratification. However, the device will be applicable for all serial optical standards, notes Dr. Paul Voois, president and CEO of ClariPhy.

The company has developed what it claims is the first digital signal processing (DSP)-based PHY for 10 Gbits/sec over multimode fiber. Its PHY "will exceed 300-m reach over legacy multimode fiber, thereby enabling a seamless and cost-effective upgrade of existing Ethernet infrastructure to 10-Gbit/sec speeds," reports Voois. "For new installations, our technology will enable the best combination of power dissipation, reach, and latency of any PHY over any cabling medium," he adds.

Sept 1, 2005, Start-up tries to breathe new life into fiber

Feb 2005, Dow Jones Venture Capital Analyst

Dec 2004, InsideChips.Ventures

Nov 9, 2004, ClariPhy Communications closes $8 million Series A round