ClariPhy Company Contact: ClariPhy Media Contact:

John O’Neill Lauri Julian

Vice President, Marketing ClariPhy Public Relations

949-922-8658 949-715-3049

john.oneill@clariphy.com l.julian@mediaconnectpr.com

CLARIPHY COMMUNICATIONS DEMONSTRATES SECOND GENERATION EDC TRANSCEIVER BASED ON MLSD TECHNOLOGY AT OFC/NFOEC 2008

Transceiver Combines Dramatic Power Reduction and Proven Performance

IRVINE, Calif., February 20, 2008 – ClariPhy Communications, Inc., a fabless semiconductor company specializing in high speed communications ICs, today announced that it will demonstrate its 10Gbit/s integrated circuits (ICs) with industry leading performance at the OFC/NFOEC conference (www.ofcnfoec.org) in San Diego, California on February 24-28, 2008. ClariPhy will showcase a second generation all-digital CMOS Maximum Likelihood Sequence Detection (MLSD) Electronic Dispersion Compensation (EDC) engine.

ClariPhy has previously demonstrated the advantage of a digital MLSD architecture for bandwidth-constrained media such as legacy multi-mode fiber in enterprise backbones. As the only supplier of 10Gbit/s MLSD based ICs, ClariPhy has leveraged the availability of advanced CMOS technologies to provide unmatched performance while meeting the stringent power budget of next generation data center and enterprise networking equipment. In contrast to non-MLSD architectures, ClariPhy’s technology uniquely offers the EDC performance enabling industry migration to low cost 10GBASE-LRM SFP+ optical module form factors. The alternative non-MLSD architectures suffer from inherent performance deficiencies as well as the variability of analog IC design, including the process dependence of device parameters, noise sensitivity, and implementation loss.

“We introduced our MLSD-based transceiver at OFC 2007 and established a new standard for 10Gbit/s EDC performance,” said Dr. Paul Voois, cofounder and CEO of ClariPhy. “Our second generation transceiver delivers even better performance at significantly lower power, demonstrating one of the key advantages of the all-digital CMOS approach, which is the exponential reduction in power and cost achievable via Moore’s Law. History has shown that all-digital CMOS is the winning technology in high-volume communications applications such as Ethernet. By delivering industry-best performance, ClariPhy has established a unique and highly differentiated advantage for 10Gbit/s EDC applications.”

ClariPhy will demonstrate its second generation MLSD technology in a private suite at the OFC/NFOEC conference (www.ofcnfoec.org) in San Diego, California on February 24-28, 2008. The demonstrations will include multi-mode and single-mode fiber applications. ClariPhy invites interested parties to contact John O’Neill, Vice President of Marketing at 949-922-8658 or john.oneill@clariphy.com.

About ClariPhy

ClariPhy Communications, Inc. is a fabless semiconductor company developing high-speed ICs targeting 10Gbit/s networks in enterprise backbone, enterprise data center and telecom environments. ClariPhy’s ICs enable IT and network management to significantly improve network performance and lower cost. ClariPhy’s investors include Norwest Venture Partners (NVP), Onset Ventures, Allegis Capital and Pacific General Ventures. ClariPhy has executive offices in Irvine, California and a development center in Cordoba, Argentina. For more information, please visit www.clariphy.com.

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